Field of the Invention
The present invention relates to the field of testing integrated logic circuits and more specifically, it relates to methods for generating test pattern fault lists for use in testing groups of logic circuits arranged in a regular structure and for determining faults in individual logic circuits within the group.
The semiconductor industry has increasingly been able, by combination of increasing density and increasing die size, to fabricate dies with increasing numbers of logic circuits per die. This has, in turn, increased the number of combinational logic circuits that must be tested in order to assure that devices without faults are not shipped to consumers.
One method of testing logic circuits used in the industry incorporates placing scan in latches before and scan out latches after the logic circuits to be tested. The placement of scan latches into the circuit is done during the design phase of die manufacture. The scan in latches have normal and test inputs and the scan out latches have normal and test outputs. During test mode, test data (in the form of a test vector of 0""s and 1""s) is clocked from a data input pin through a chain of scan in latches, then through the combinational logic to a chain of scan out latches. The latches are xe2x80x9cchainedxe2x80x9d by connecting the test mode inputs together and by connecting the test mode outputs together. The data, which may be altered by the combinational logic, is then clocked out to a test output pin. During normal operation, the test clocks are held off, allowing the normal inputs on the scan in latches to be clocked through the combinational logic to the normal scan out latch outputs.
An important component of the scan chain test methodology described above is the step of generating the test data to apply to the combinational logic through the scan in latches. Several concerns arise when generating the test data, including the number of test vectors and size of each test vector required for any given scan chain/combinational logic subset. Corollary concerns for physical testing include the amount of tester time required to execute each test vector and the amount of tester buffer memory consumed by the tests. Both these corollary concerns increase as the number of logic circuits per die increase and therefore increase the cost of testing.
As an aid to understanding the testing of a logic circuit an exemplary circuit will be used. This same circuit will be used in describing the operation of the present invention. In this example individual logic circuits are assumed to be latch circuits and the combinational logic is in the form of an array of the latches, plus the combinational logic corresponding to latch row address decode and selection.
Referring to the drawings, FIG. 1 illustrates an exemplary regular structure logic array. Logic array 100 is a four bit (columns) by eight address (rows) array comprised of sixty four scannable latches. In logic array 100 latches 105A1, 105B1, 105C1, and 105D1 are arranged in a first row 111, latches 105A2, 105B2, 105C2, and 105D2 are arranged in a second row 112, latches 105A3, 105B31, 105C3, and 105D3 are arranged in a third row 113, latches 105A4, 105B4, 105C4, and 105D4 are arranged in a fourth row 114, latches 105A5, 105B5, 105C5, and 105D5 are arranged in a fifth row 115, latches 105A6, 105B6, 105C6, and 105D6 are arranged in a sixth row 116, latches 105A7, 105B7, 105C7, and 105D7 are arranged in a seventh row 117 and latches 105A8, 105B8, 105C8, and 105D8 are in arranged an eighth row 118 of the logic array. Each column in logic array 100 corresponds to a bit position and each row to an address where the bits are stored.
Test data in the form of a stream of 0""s and 1""s from external combinational logic enters logic array 100 through an input bus 120. The address to which the test data is written is selected by applying a write address to write bus 125. The write address contains a bit pattern that corresponds to one of the address rows in logic array 100. The write address is passed into selector 130, which directs a write signal to each row of array 100 as determined by decode of each write address value. Each write signal is then passed to one of individual AND gates 135A, 135B, 135C, 135D, 135E, 135F, 135G and 135H. Gate 135A is coupled to row 111, gate 135B to row 112, gate 135C to row 113, gate 135D to row 114, gate 135E to row 115, gate 135F to row 116, gate 135G to row 117 and gate 135H to row 118 of logic array 100. An enable signal 140 applied to all AND gates 135A through 135H, allows the data to be written to the selected address. Data is read out of the logic array via an array output bus 145. The row to be read out is determined by decode of a read address applied to a multiplexer 150 and the data is then passed through multiplexer 150 to data out bus 155. The read address contains a bit pattern that corresponds to one of the address rows in logic array 100. The read address is passed into multiplexer 150, which directs data from the corresponding row of array 100 to data out bus 155. The read address is passed to multiplexer 150 through a read bus 160.
To test a scannable latch within array 100, test data in the form of a test bit pattern is applied to input bus 120 and a write address is applied to write bus 125 to write the test bit pattern to the latch. The test bit pattern used is a function of the design of the latch. The content of the latch is read out by applying a corresponding read address to read bus 150. The read bit pattern is then compared to an expected bit pattern. If the read bit pattern agrees with the expected bit pattern then the latch passes. If the read bit pattern does not agree with the expected bit pattern then the latch fails the test.
To completely test logic array 100, a test bit pattern fault on a I and test bit pattern fault on a 0 must be written to each latch. Thus one hundred and twenty eight test patterns (sixty four fault on 1""s and sixty four fault on 0""s) must be applied to logic array 100. Each test pattern must be associated with the address of the latch to ensure the test pattern is written to the intended latch and expected pattern data is read out of the intended latch. A test pattern generator creates the test patterns. A tester then applies the test patterns to circuit under test.
However, in the case of exemplary logic array 100, the test pattern generator is unaware of the regularity of the logic array and will determine a test pattern for each latch. Another way of stating this is the test pattern generator will create a test pattern for each of the four bit positions in a row of logic array 100 independently of the other bit positions. For example the test pattern for latch 105A may be the 1st test applied to logic array 100 by the tester, while the test pattern for latch 105B may be the 27th test applied to logic array 100 by the tester. Thus the tester, which reads the test patterns and sets up the write addresses to apply to write bus 125 and the read addresses to apply to read bus 160 based on the address of the latch to be tested sets up the same read and write addresses multiple times. This causes increased test setup time and thus overall test time. In the case where the test patterns are stored before the test is actually applied, the number of test patterns required directly effects the amount of tester buffer memory required.
A first aspect of the present invention is a method of testing a circuit having multiple elements, comprising the steps of: creating a plurality of faults representing the elements for testing the circuit; grouping the faults based on common attributes of the faults; creating a test pattern for each group of faults; and testing the circuit with the test patterns.
A second aspect of the present invention is a method of testing a circuit having multiple elements, comprising the steps of: determining which elements are attributable; associating an attribute with each attributable element to create an attributed element; adding the attributed elements to a fault list; generating a corresponding test pattern for each attributed element; selecting a previously unselected attributed element from the fault list; selecting all other attributed elements associated with the same attribute as the selected element, combining corresponding test patterns for each attributed element associated with the same attribute to create a combined test pattern and testing the circuit using the combined test pattern in order to simultaneously test all attributable elements having the same attribute; and repeating creation of combined test patterns and testing of the circuit until all attributed elements in the fault list have been selected.
A third aspect of the present invention is a method of testing a circuit having multiple elements, comprising the steps of: determining which elements are attributable; associating an attribute with each attributable element to create an attributed element; adding the attributed elements to a fault list; generating a corresponding test pattern for each attributed element; selecting a previously unselected attributed element from said fault list; selecting all other attributed elements associated with the same attribute as the selected element, combining corresponding test patterns for each attributed element associated with said same attribute to create a combined test pattern and storing said combined test pattern in a tester memory; and repeating creation and storing of combined test patterns in tester memory until all attributed elements in the fault list have been selected; and testing said circuit using the combined test patterns stored in the tester memory in order to simultaneously test all attributable elements having the same attribute.